SY89874U buffer equivalent, programmable clock divider/fanout buffer.
* Integrated programmable clock divider and 1:2 fanout buffer
* Guaranteed AC performance over temperature and voltage: − >2.5GHz fMAX − <250ps tr/tf − <15ps with.
The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously.
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed v.
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